Numerous applications exist in semiconductor processing in which it is desired to form planarized surfaces over uneven topography. The planarized surfaces will typically not be absolutely planar in a mathematical sense, but rather will be approximately planar in that there can be minor variations across the surfaces which cause the surfaces to deviate from absolute planarity. Such minor variations can include, for example, dishing, which is a common occurrence if chemical-mechanical polishing (CMP) is utilized for the planarization of a surface. The term “substantially planar” is utilized herein to indicate that a surface has only minor variations from absolute planarity, with typical minor variations being within about +/−5% from absolute planarity.
One method for forming a planarized surface is as follows. Initially, a single material is deposited over a non-planar topography. The material is deposited to a sufficient thickness so that the material completely covers and fills the non-planar topography of the substrate. An upper surface of the material will typically be non-planar as-deposited, in that the material will deposit over the non-planar topography of the substrate with some conformality. The material is subsequently planarized with an appropriate process, such as, for example, chemical-mechanical polishing (CMP) to substantially planarize the upper surface of the material.
A problem with planarization of a single material is that it is difficult to ascertain an appropriate stop point within the material. For instance, if CMP is utilized, a rate of removal of the material by the CMP can be estimated, and the CMP can then be timed in an attempt to remove a desired thickness of the material. However, minor variations in temperature, type of slurry, polishing pad wear, etc. can impact the rate of removal of material by CMP. Accordingly, the rate of removal of the material by the CMP can vary as the various components utilized in the polishing process age, and/or if temperature varies. This can make it difficult to control CMP processes within the tight tolerances desired for modern semiconductor device processing.
If the CMP process is not appropriately maintained within desired tolerances, there can be a non-uniform thickness of material across the substrate after the CMP, which can create difficulties in fabrication steps following the CMP.
It is desired to develop new methods for forming planarized surfaces over semiconductor substrates to alleviate the problems discussed above.